1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly to a fully differential operational amplifier having a high common mode feedback gain.
2. Description of the Prior Art
Fully differential operational amplifiers are known which comprise initial and drive stages. As shown in FIG. 1 of the accompanying drawings, the initial stage of such a fully differential operational amplifier comprises a constant-current regulated power supply Il, P channel MOS transistors M41, M42 having respective sources connected to the constant-current regulated power supply Il and serving as an input transistor pair, and N channel MOS transistors M43, M44 connected to the respective drains of the P channel MOS transistors M41, M42 and serving as a load. The drive stage of the fully differential operational amplifier comprises P channel MOS transistors M47, M48, and N channel MOS transistors M45, M46 having respective drains connected to the P channel MOS transistors M47, M48. A common mode feedback loop for keeping noninverted and inverted common mode voltages at a constant level is composed of a circuit for generating the average of noninverted and inverted output voltages and a feedback loop for connecting the output from the circuit to the gates of the P channel MOS transistors M47, m48. When the voltage at a noninverting input terminal IN+ is higher than the voltage at an inverting input terminal IN-, the current flowing through the N channel MOS transistor M44 is less than the current flowing through the N channel MOS transistor M43. Therefore, the gate voltage of the N channel MOS transistor M46 is lower than the gate voltage of the N channel MOS transistor M45, and the noninverted output voltage is higher than the inverted output voltage.
The noninverted and inverted common mode voltages are fixed at intermediate points of first and second power supply terminals 41, 42 for supplying a power supply voltage Vcc therebetween. These fixed voltages are realized by the common mode feedback loop as follows: the circuit arrangement is designed such that the noninverted and inverted common mode voltages are the same as the potentials at the intermediate point of the first and second power supply terminals when a fixed potential Vc of the constant-current regulated power supply Il is equalized to the power supply voltage Vcc. In FIG. 4, the potential at a terminal Vb' becomes (Vout+ +Vout-) -5+Vb when the power supply voltages are 0V and 5V. The potential at a terminal Vb may be selected such that a negative feedback loop operates to equalize (Vout++Vout-)-5 to 0 by connecting the terminal Vb' shown in FIG. 4 to the terminal Vb, shown in FIG. 1, making it possible to equalize the average (common mode voltage) of the noninverted and inverted output voltages to 2.5 V.
The operational amplifier shown in FIG. 1 is, however, disadvantageous in that the feedback gain of the common mode feedback circuit for keeping noninverted and inverted common mode voltages at a constant level is determined only by the gain of the inverter circuit composed of the P channel MOS transistors M47, M48 and the N channel MOS transistors M45, M46, and is at most about 20 dB.
Another disadvantage is that the fall time of the output signal is limited and delayed by the mutual conductance gm of the P channel MOS transistors in the case where a capacitive element is used as the load.
A further disadvantage is that the DC gain of the initial stage is governed by the product of the mutual conductance gm of the P channel MOS transistors M41, M42 and the initial stage output resistance determined by the N channel MOS transistors M43, M44, and is reduced in inverse proportion to the square root by increasing the initial stage current in order to increase the GB product.